library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity traffic_light is
    port(clk: in std_logic;
        reset: in std_logic;
        rl,gl,yl: out std_logic;
        counter_time: out std_logic_vector(15 downto 0));
end traffic_light;

architecture behave of traffic_light is
    signal mtime: integer range 0 to 10;
begin
    process(clk,reset)
        type state_type is (R,G,Y);
        variable state: state_type;
    begin
        if clk'event and clk = '1' then
            case state is
                when R => rl <= '1'; 
                    gl <= '0';
                    yl <= '0';
                    mtime <= mtime-1;
                    counter_time <= conv_std_logic_vector(mtime, 16);
                    if(mtime = 1) then 
                        state := G;
                        mtime <= 10;
                    else
                        state := R;
                    end if;
                    
                when G => gl <= '1';
                    rl <= '0';
                    yl <= '0';
                    mtime <= mtime-1;
                    counter_time <= conv_std_logic_vector(mtime, 16);
                    if(mtime = 1) then
                        state := Y;
                        mtime <= 3;
                    else
                        state := G;
                    end if;
                    
                when Y => yl <= '1';
                    gl <= '0';
                    rl <= '0';
                    mtime <= mtime-1;
                    counter_time <= conv_std_logic_vector(mtime, 16);
                    if(mtime = 1) then
                        state := R;
                        mtime <= 10;
                    else
                        state := Y;
                    end if;
            end case;
        end if;
    end process;
end behave;
